SHAKTI vs AJIT

 

                Researchers at IIT Bombay develop the country’s first indigenously designed and fabricated microprocessor.

                A microprocessor is an integrated circuit (IC) that contains a few millions of transistors (semiconductor-based electronic devices) fused on a semiconductor chip. It is just a few millimetres in dimension and is used in almost every electronic device—from the microwave and washing machine in homes to advanced supercomputers of a space station. However, developing and manufacturing a microprocessor is not easy—it is expensive, risky and needs much skill. Hence, only a handful of companies across the world have been able to manufacture and sell microprocessors successfully. 

                 In an attempt to make a mark in the highly competitive segment of microprocessor manufacturing, engineers from the Indian Institute of Technology Bombay (IIT Bombay) have developed a new microprocessor called AJIT—the first ever microprocessor to be conceptualised, designed, developed and manufactured in India. This innovation could not only reduce the country’s imports but also make India self-reliant in electronics.

            AJIT comes with an arithmetic logic unit that can do basic arithmetic and logical operations like addition, subtraction and comparison, and a memory management unit that stores and retrieves data from memory. There is also a floating point unit designed to handle calculations with non-integer numbers efficiently. For those who would like to program the microprocessor, there is a hardware debugger unit to help them monitor and control the processor.

            A processor made in India offers more than just the cost benefits. It provides the country with autonomy and self-reliance in the electronics sector and reduces our dependence on technology imported from other parts of the world. It also ensures a secure system with no opportunity for any backdoor entry, thus preventing digital sabotage by other countries or malicious organisations. So far, though we have had Indian teams design complete processors in India, no Indian company owns a commercially available microprocessor product. AJIT hopes to change that soon.

Shakti vs Ajit

            Shakti the first microprocessor designed and developed by IIT Madras where as Ajit is developed at IIT Bombay.

            Shakti is developed as a built in microprocessor which can be deliberately used in mobile computing and wireless devices.where as Ajit is used in the microwave and washing machine in homes to advanced supercomputers of a space station.

            The C-class processor of Shaksti works at clock frequency of 1.5 GHz and i-class ranges froom 1.5 to 2.0GHz. where as the AJIT can run one instruction per clock cycle and can operate at clock speeds between 70-120MHz, comparable to its competitors in the market.

            Shakti is one of the few open-source Microprocessor’s available in electronic markets.The researchers have made the software tools associated with Ajit freely available to everyone.The processor is also available as a ‘softcore’, where vendors can buy a license to use the design of the microprocessor and fabricate it to use it in their system. The researchers also offer to customise the processor for specific applications. The design of the processor is modular, and at some extra cost, vendors can get a processor design with a feature set suitable for the system they are designing.

SHAKTI processor is much smaller in size as compared to AJIT that is Shakti is typical microprocessor aimed to used in smartphones and other netwoeking devices,where as Ajit being bigger, is aimed at larger systems such as robotics and automation systems.

            Shakti is completely designed on new RISC-V ISA (Instruction set architecture),Where as the The AJIT microprocessor uses SPARC ISA architecture. SPARC (Scalable Processor Architecture) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems.

            RIMO is the code name of the SHAKTI C-class based SoC (System on a Chip) with size of 144 sq.mm.where as  In the first stage, AJIT has been manufactured in the government-owned Semiconductor Laboratory (SCL), Chandigarh, with a technology that offers the smallest building block of the size 180 nanometers.

            Both shakti and Ajit have their own good features.

Similar Development

            Furthermore, it is worth mentioning, India has also developed its first RISC-V based processor Shakti last year. A team of researchers and students from Indian Institute of Technology (IIT) Madras have developed this chip and made the design open-sourced. The chip is clocking at 400MHz speed and a majority of the front-end design is done using verilog. The Shakti Project includes a family of six types of microprocessors and has been broadly categorised into base processors, multi-core processors and experimental processors. This chip is basically aimed in using towards smartphones and the Internet of Things (IoT) devices.

This blog is for academic activity.
Author - Mayuresh Patil

6 Variants of SHAKTI

 

Base Class Of Processors

E-class:

                    The E-class is 32/64 bit microcontrollers capable of supporting all extensions of RISC-V ISA, aimed at low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM’s M-class (CorTex-M series) cores. 

                 E-arty35T is an SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 General Purpose Input Output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a Platform Level Interrupt Controller (PLIC), a Counter, 2 Serial Peripheral (SPI), 2 Universal Asynchronous Receiver Transmitter (UART), 1 Inter-Integrated Circuit (I2C), 6 Pulse Width Modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC).

Supported operating Systems:

• FreeRTOS
• Zephyr 
• eChronos

Application domain of E-class:

• Smart-cards
•  IoT devices
•  motor controls and robotic platforms.

C-class:

                    The C-class is a 64-bit controller class of processor, aimed at mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It targets the mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. 

                    C-arty100T is a SoC build around C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I2C). It is aimed at mid-range application workloads with a very low power consumption and has support for optional memory protection.

Micro architecture-

Supported operating Systems:

• Linux
• Sel4

Application domain of C-class:

• embedded systems
• motor-control
• Internet of things
• storage
• Industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc.

I-class:

                   I-Class is a superscalar out-of-order (OoO) processor with potential applications in general purpose computing and high-end embedded markets.

                The I-class is a 64-bit processor which targets the compute, mobile, storage and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The operational clock frequency of this processor is 1.5-2.5 GHz. The team is currently working on implementing atomics, Memory dependence prediction, Instruction Window/Scheduler optimizations, Implementation of some functional units, Performance analysis/projections, Optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor.

Basic I-class Pipeline-

Multicore Processors

M-class:

                    A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are aimed at general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance targets.

                    Tile-Link is used as the cache-coherent interconnect used along with transaction adapters/bridges to AXI4/AHB to connect to fast and/or slow peripherals. The TileLink topology is customizable to allow optimizations for various power/performance targets. In typical configurations, it is expected that a core complex of 2 or 4 cores will share an L2 cache. L3 caches are optional and are typically expected to be used in desktop type applications.    

S-class:

                The S-Class is a 64-bit superscalar, multi-threaded variant aimed at Desktop and Enterprise server Application. Its supports 2-16 cores with a clock frequency of about 1.2–3 GHz.

            Aimed at Workstation and Enterprise server workloads. The base core is an enhanced version of the I-class, with quad-core and multi-threading support. A tile-link based cache coherent mesh fabric is the interconnect of choice. Cores are expected to use dedicated L2 caches and segmented L3 caches. A maximum core count of 32 will be supported. External interconnect is expected to be Gen-Z and we are considering supporting multi-socket cache coherency based on a MOESIF style protocol running on top of Gen-Z.

H-class:

                The H-class is a 64-bit processor aimed at highly parallel enterprise, HPC and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.

            A SoC configuration aimed at highly parallel enterprise, HPC and analytics workloads. The cores can be a combination of C or I class, single thread performance driving the core choice. Optional L4 caches and an optimized memory hierarchy to achieve a high memory bandwidth. The architecture thrust is on accelerators, VPU and AI/ML and an mesh SoC fabric optimized for up to 128 cores with multiple accelerators per core. Close integration with an external Gen-Z fabric is a key part of the design, as is support for storage class memory.

Experimental Processors

        There are 2 experimental/research projects which focus on developing a high security and fault tolerant processor.

T-class:

              The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks.

F-class:

                    Fault tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.

This blog is for academic activity.

Author- Suraj Patil

References

India's First Indigenous Microprocessor!

            The SHAKTI Processor Program, was started as an academic initiative back in 2014 by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT-Madras. It is completely Open-source. The major aim is to bridge the gap between academia and industry, to provide innovative and customized solutions.

What is SHAKTI?

                SHAKTI is an open-source initiative by the RISE group at IIT Madras. Shakti is building many processors based on the RISC-V instruction set.  The processors are based on 22nm FINFET technology. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors". They currently have 3 core variants known as the E class , C class and I class. E class is for embedded application like robotic controller boards and IoT boards. C class is the controller class for mobile like applications and can run at upto 1.5 GHz. I class is the performance oriented and can run at around 2.5 Ghz clock speed . They also have plans for multi core processors that will involve combinations of C class cores and I class cores .They also have plans for a super computer class processor which will be called Parallel shakti or para shakti.

                These chips could be used in ISRO’s NavIC satellites in the future. C class cores will mostly compete with ARM . The one who design chips inside your phones . Companies like Qualcomm, Samsung and MediaTek use these designs .you must have heard words like cortex A57 or something similar. These are designed by ARM. More on that later .  2 C class processors were fabricated . One by intel based on 22 nm called RISECREEK  and the special one in India at the Chandigarh facility partly run by ISRO based on 180 nm called RIMO.

RISC-V ISA Overview

                RISC-V (pronounced “risk-five”) is a free and open Instruction Set Architecture (ISA) enabling a new era of processor innovation through open standard collaboration. RISC-V was originally designed to support computer architecture research and education. But now it has become a standard free and open architecture for industry implementations. RISC-V ISA is defined as a base integer ISA, which must be present in any implementation, plus optional extensions to the base ISA. Each base integer instruction set is characterized by the width of the integer registers and the corresponding size of the address space and by the number of integer registers. RISC-V is little-endian and comes in 32 and 64 bit flavors. For both, int is 32 bits. Pointers and long are of native register size. Signed values are always sign extended in a larger register. Unsigned 8/16-bit values are zero extended. Unsigned 32-bit values are sign-extended. RISC-V has been designed to support extensive customization and specialization. RISC-V spec has two volumes, User level Spec and Privilege level Spec.

 

Why is Shakti different ?

            Mainly because it uses the open source RISC-V instruction architecture . Intel/ AMD and ARM have their own architectures or the language with which you communicate with the processor . Intel and AMD has something called X86 and ARM uses their own . They do not share this with anyone  .If you reverse engineer and make one you will have to deal with court cases .

            RISC-V is an open source instruction  set architecture .Suppose you go to buy a car , but you are forced to buy a truck along with it . If you want to buy a car , you have to also buy the truck . This is the problem with INTEL and ARM . You cant choose what specific instructions you want to use . You have to buy them all . We can use RISC-V to make a custom chip design for our needs . As a bonus many people responsible for RISC-V are also Indian. They also have their own company called sci-five which makes designs like Shakti . The startup coming out from IIT Madras will be called InCore. Keep a note of that , will require after some time .This advantage gives us the power to design the chips of our need with good security . Will detail this later .

Applications 

The E and C-classes are the first set of indigenous processors aimed at :

• Internet of Things (IoT)
• Embedded 
• Desktop markets.

The SHAKTI project aims to build 6 variants of processors based on the RISC-V ISA....

This blog is for academic activity.

Author- Samiksha Nalamwar

References