6 Variants of SHAKTI

 

Base Class Of Processors

E-class:

                    The E-class is 32/64 bit microcontrollers capable of supporting all extensions of RISC-V ISA, aimed at low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM’s M-class (CorTex-M series) cores. 

                 E-arty35T is an SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 General Purpose Input Output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a Platform Level Interrupt Controller (PLIC), a Counter, 2 Serial Peripheral (SPI), 2 Universal Asynchronous Receiver Transmitter (UART), 1 Inter-Integrated Circuit (I2C), 6 Pulse Width Modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC).

Supported operating Systems:

• FreeRTOS
• Zephyr 
• eChronos

Application domain of E-class:

• Smart-cards
•  IoT devices
•  motor controls and robotic platforms.

C-class:

                    The C-class is a 64-bit controller class of processor, aimed at mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It targets the mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. 

                    C-arty100T is a SoC build around C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I2C). It is aimed at mid-range application workloads with a very low power consumption and has support for optional memory protection.

Micro architecture-

Supported operating Systems:

• Linux
• Sel4

Application domain of C-class:

• embedded systems
• motor-control
• Internet of things
• storage
• Industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc.

I-class:

                   I-Class is a superscalar out-of-order (OoO) processor with potential applications in general purpose computing and high-end embedded markets.

                The I-class is a 64-bit processor which targets the compute, mobile, storage and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep pipeline stages. The operational clock frequency of this processor is 1.5-2.5 GHz. The team is currently working on implementing atomics, Memory dependence prediction, Instruction Window/Scheduler optimizations, Implementation of some functional units, Performance analysis/projections, Optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor.

Basic I-class Pipeline-

Multicore Processors

M-class:

                    A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are aimed at general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance targets.

                    Tile-Link is used as the cache-coherent interconnect used along with transaction adapters/bridges to AXI4/AHB to connect to fast and/or slow peripherals. The TileLink topology is customizable to allow optimizations for various power/performance targets. In typical configurations, it is expected that a core complex of 2 or 4 cores will share an L2 cache. L3 caches are optional and are typically expected to be used in desktop type applications.    

S-class:

                The S-Class is a 64-bit superscalar, multi-threaded variant aimed at Desktop and Enterprise server Application. Its supports 2-16 cores with a clock frequency of about 1.2–3 GHz.

            Aimed at Workstation and Enterprise server workloads. The base core is an enhanced version of the I-class, with quad-core and multi-threading support. A tile-link based cache coherent mesh fabric is the interconnect of choice. Cores are expected to use dedicated L2 caches and segmented L3 caches. A maximum core count of 32 will be supported. External interconnect is expected to be Gen-Z and we are considering supporting multi-socket cache coherency based on a MOESIF style protocol running on top of Gen-Z.

H-class:

                The H-class is a 64-bit processor aimed at highly parallel enterprise, HPC and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.

            A SoC configuration aimed at highly parallel enterprise, HPC and analytics workloads. The cores can be a combination of C or I class, single thread performance driving the core choice. Optional L4 caches and an optimized memory hierarchy to achieve a high memory bandwidth. The architecture thrust is on accelerators, VPU and AI/ML and an mesh SoC fabric optimized for up to 128 cores with multiple accelerators per core. Close integration with an external Gen-Z fabric is a key part of the design, as is support for storage class memory.

Experimental Processors

        There are 2 experimental/research projects which focus on developing a high security and fault tolerant processor.

T-class:

              The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks.

F-class:

                    Fault tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.

This blog is for academic activity.

Author- Suraj Patil

References